~ruther/verilog-riscv-semestral-project: programs 181e94c4c368df49b63ee435f623436482f2f6a2

~ruther/verilog-riscv-semestral-project

ref: 181e94c4c368df49b63ee435f623436482f2f6a2 verilog-riscv-semestral-project/programs d---------

6ce1c838 — Rutherther 1 year, 7 months ago

chore: remove gcc generated file

30a7f949 — Rutherther 1 year, 7 months ago

feat: add basic testing programs