~ruther/verilog-riscv-semestral-project: src/cpu_types.sv 057ee98bbecfb8a284b67bef50b04b70ae18e220

~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 2 years ago

chore: add cpu types for various sources

Better orientation by name instead of
number