From aeab403896e168bc0c44a65883d46bb96689b7fb Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Sun, 10 Dec 2023 09:50:04 +0100
Subject: [PATCH] feat: add forwarding signal for better debugging

---
 src/forwarder.sv     | 5 +++++
 src/stages/decode.sv | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/src/forwarder.sv b/src/forwarder.sv
index 4ca0bd0..5e3b5b8 100644
--- a/src/forwarder.sv
+++ b/src/forwarder.sv
@@ -6,6 +6,7 @@ module forwarder(
   input [31:0]      register_file_data,
   input             forwarding_data_status_t data_in_pipeline,
 
+  output            forwarding,
   output reg        stall,
   output reg [31:0] data
 );
@@ -17,18 +18,22 @@ module forwarder(
   always_comb begin
     stall = 0;
     data = register_file_data;
+    forwarding = 0;
 
     if (read_address != 0 && data_in_pipeline.execute_out.address == read_address) begin
       stall = !data_in_pipeline.execute_out.valid;
       data = data_in_pipeline.execute_out.data;
+      forwarding = 1;
     end
     else if (read_address != 0 && data_in_pipeline.access_out.address == read_address) begin
       stall = !data_in_pipeline.access_out.valid;
       data = data_in_pipeline.access_out.data;
+      forwarding = 1;
     end
     else if (read_address != 0 && data_in_pipeline.writeback_in.address == read_address) begin
       stall = !data_in_pipeline.writeback_in.valid;
       data = data_in_pipeline.writeback_in.data;
+      forwarding = 1;
     end
   end
 endmodule
diff --git a/src/stages/decode.sv b/src/stages/decode.sv
index c2faed2..7a99c4f 100644
--- a/src/stages/decode.sv
+++ b/src/stages/decode.sv
@@ -96,6 +96,7 @@ module decode(
     .register_file_data(reg_rd1),
     .data_in_pipeline(data_in_pipeline),
     .stall(stall_1),
+    .forwarding(),
     .data(forwarded_reg_rd1)
   );
 
@@ -105,6 +106,7 @@ module decode(
     .register_file_data(reg_rd2),
     .data_in_pipeline(data_in_pipeline),
     .stall(stall_2),
+    .forwarding(),
     .data(forwarded_reg_rd2)
   );
 
-- 
2.48.1