~ruther/jesd204b-vhdl

ref: 3e9599ef10eead139b55c2e9fd5b67d60b998ef7 jesd204b-vhdl/src/data_link/link_controller.vhd -rw-r--r-- 6.4 KiB
3e9599ef — Rutherther 2 years ago
Merge pull request #25 from Rutherther/feat/subclass-1-support

Add subclass 1 support
6ac19e82 — František Boháček 2 years ago
feat: change behavior of asserting link nsynced only on frame clk (subclass 0) and multiframe clk (subclass 1)
92031bce — František Boháček 2 years ago
fix: deassert sync on LMFC falling edge to match the standard
6b1d2bde — František Boháček 2 years ago
feat: add basic subclass 1 support
212264ba — František Boháček 2 years ago
chore: specify ranges for all integers

Ranges are not needed inside of tesbenches.
Resolves #22.
f077b173 — František Boháček 2 years ago
feat: assume full synchronization after 4 correct 8b10b characters are received after 4 /K/ characters

Resolves #23.
3a90bcd7 — František Boháček 2 years ago
feat: make sync aligned to frame clock

Resolves #21
7f624c75 — František Boháček 2 years ago
feat: move all link configuration to generic instead of ports

Configuration is same for one compilation, it cannot change.
Thus it does not make sense to be a port.
Resolves #13.
87f51b4a — František Boháček 2 years ago
chore: add documentation to the code
186db205 — František Boháček 2 years ago
feat(link): add link controller
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