M src/data_link/data_link_layer.vhd => src/data_link/data_link_layer.vhd +9 -6
@@ 94,11 94,12 @@ begin -- architecture a1
-- error handling
error_handling : entity work.error_handler
+ generic map (
+ F => F)
port map (
ci_char_clk => ci_char_clk,
ci_reset => ci_reset,
ci_state => link_controller_co_state,
- ci_F => F,
di_char => decoder_do_char,
ci_config => ERROR_CONFIG,
ci_lane_alignment_error => lane_alignment_co_error,
@@ 111,12 112,13 @@ begin -- architecture a1
-- link controller
link_controller : entity work.link_controller
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => ci_char_clk,
ci_reset => ci_reset,
ci_resync => link_controller_ci_resync,
- ci_F => F,
- ci_K => K,
ci_lane_alignment_error => lane_alignment_co_error,
ci_lane_alignment_aligned => lane_alignment_co_aligned,
ci_lane_alignment_ready => lane_alignment_co_ready,
@@ 146,11 148,12 @@ begin -- architecture a1
-- lane alignment
lane_alignment : entity work.lane_alignment
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => ci_char_clk,
ci_reset => ci_reset,
- ci_F => F,
- ci_K => K,
ci_state => link_controller_co_state,
ci_realign => lane_alignment_ci_realign,
co_ready => lane_alignment_co_ready,
@@ 164,7 167,7 @@ begin -- architecture a1
generic map (
SCRAMBLING => SCRAMBLING,
F => F,
- K => K)
+ K => K)
port map (
ci_char_clk => ci_char_clk,
ci_frame_clk => ci_frame_clk,
M src/data_link/error_handler.vhd => src/data_link/error_handler.vhd +1 -1
@@ 79,7 79,7 @@ begin -- architecture a1
co_request_sync <= reg_request_sync;
active <= '1' when di_char.user_data = '1' and ci_state /= INIT else '0';
next_index <= 0 when active = '0' else
- (reg_index + 1) mod ci_F;
+ (reg_index + 1) mod F;
next_request_sync <= '0' when active = '0' else
'1' when reg_request_sync = '1' else
M src/data_link/ilas_parser.vhd => src/data_link/ilas_parser.vhd +3 -4
@@ 14,6 14,8 @@ use ieee.numeric_std.all;
entity ilas_parser is
generic (
+ F : integer; -- Number of octets in a frame
+ K : integer; -- Number of frames in a multiframe
K_character : std_logic_vector(7 downto 0) := "10111100"; -- Character
-- for syncing
R_character : std_logic_vector(7 downto 0) := "00011100"; -- ILAS
@@ 30,9 32,6 @@ entity ilas_parser is
port (
ci_char_clk : in std_logic; -- Character clock
ci_reset : in std_logic; -- Reset (asynchonous, active low)
- ci_F : in integer range 0 to 256; -- Number of octets in a
- -- frame
- ci_K : in integer range 0 to 32; -- Number of frames in a multiframe
ci_state : in link_state; -- State of the lane
di_char : in character_vector; -- Character from 8b10b decoder
do_config : out link_config; -- Config found in ILAS
@@ 90,7 89,7 @@ architecture a1 of ilas_parser is
return data(up_index - 7 + bit_index);
end function getBitByIndex;
begin -- architecture a1
- octets_in_multiframe <= ci_F * CI_K;
+ octets_in_multiframe <= F * K;
-- ILAS
-- one multiframe is sent
-- 4 frames in a multiframe
M src/data_link/lane_alignment.vhd => src/data_link/lane_alignment.vhd +2 -4
@@ 15,6 15,8 @@ use work.data_link_pkg.all;
entity lane_alignment is
generic (
+ F : integer; -- Number of octets in a frame
+ K : integer; -- Number of frames in a multiframe
buffer_size : integer := 256; -- How many octets to keep
alignment_character : std_logic_vector(7 downto 0) := "01111100"; -- The K
--
@@ 30,10 32,6 @@ entity lane_alignment is
ci_state : in link_state; -- State of the lane
ci_realign : in std_logic; -- Whether to realign to the last
-- found alignment character
- ci_F : in integer range 0 to 256; -- Number of octets in
- -- a frame
- ci_K : in integer range 0 to 32; -- Number of frames in
- -- a multiframe
di_char : in character_vector; -- Character from 8b10b decoder
co_ready : out std_logic; -- Whether /A/ was received and
-- waiting for start
M src/data_link/link_controller.vhd => src/data_link/link_controller.vhd +5 -5
@@ 20,6 20,8 @@ use work.data_link_pkg.all;
entity link_controller is
generic (
+ F : integer; -- Number of octets in a frame
+ K : integer; -- Number of frames in a multiframe
K_character : std_logic_vector(7 downto 0) := "10111100"); -- Sync character
port (
ci_char_clk : in std_logic; -- Character clock
@@ 28,9 30,6 @@ entity link_controller is
do_config : out link_config; -- Config found in ILAS
- ci_F : in integer range 0 to 256; -- Number of octets in a frame
- ci_K : in integer range 0 to 32; -- Number of frames in a multiframe
-
ci_lane_alignment_error : in std_logic; -- Signals a problem with lane
-- alignment in this data link
-- (see lane alighnment component)
@@ 71,11 70,12 @@ architecture a1 of link_controller is
signal ilas_unexpected_char : std_logic := '0';
begin -- architecture a1
ilas: entity work.ilas_parser
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => ci_char_clk,
ci_reset => ci_reset,
- ci_F => ci_F,
- ci_K => ci_K,
ci_state => reg_state,
di_char => di_char,
do_config => do_config,
M testbench/data_link/ilas_parser_tb.vhd => testbench/data_link/ilas_parser_tb.vhd +3 -2
@@ 249,11 249,12 @@ architecture a1 of ilas_parser_tb is
begin -- architecture a1
uut: entity work.ilas_parser
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => clk,
ci_reset => reset,
- ci_F => F,
- ci_K => K,
ci_state => ci_state,
di_char => di_char,
do_config => do_config,
M testbench/data_link/lane_alignment_tb.vhd => testbench/data_link/lane_alignment_tb.vhd +3 -2
@@ 65,11 65,12 @@ architecture a1 of lane_alignment_tb is
begin -- architecture a1
uut : entity work.lane_alignment
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => clk,
ci_reset => reset,
- ci_F => F,
- ci_K => K,
ci_start => ci_start,
ci_state => ci_state,
di_char => di_char,
M testbench/data_link/link_controller_tb.vhd => testbench/data_link/link_controller_tb.vhd +3 -2
@@ 216,11 216,12 @@ architecture a1 of link_controller_tb is
begin -- architecture a1
uut : entity work.link_controller
+ generic map (
+ F => F,
+ K => K)
port map (
ci_char_clk => clk,
ci_reset => reset,
- ci_F => F,
- ci_K => K,
ci_resync => ci_resync,
ci_lane_alignment_aligned => ci_lane_alignment_aligned,
ci_lane_alignment_error => ci_lane_alignment_error,