3 files changed, 34 insertions(+), 26 deletions(-)

M src/data_link/data_link_layer.vhd
M src/data_link/link_controller.vhd
M src/jesd204b_link_rx.vhd

@@ 37,7 37,6 @@ entity data_link_layer is
   port (
     ci_char_clk       : in std_logic;   -- Character clock
     ci_frame_clk      : in std_logic;   -- Frame clock
-    ci_multiframe_clk : in std_logic;
     ci_reset          : in std_logic;   -- Reset (asynchronous, active low)
 
     -- link configuration


@@ 124,7 123,6 @@ begin  -- architecture a1
       F => F,
       K => K)
     port map (
-      ci_multiframe_clk          => ci_multiframe_clk,
       ci_frame_clk               => ci_frame_clk,
       ci_char_clk                => ci_char_clk,
       ci_reset                   => ci_reset,

@@ 25,7 25,6 @@ entity link_controller is
     K           : integer range 1 to 32;  -- Number of frames in a multiframe
     K_character : std_logic_vector(7 downto 0) := "10111100");  -- Sync character
   port (
-    ci_multiframe_clk : in std_logic;   -- Multiframe clock
     ci_frame_clk      : in std_logic;   -- Frame clock
     ci_char_clk       : in std_logic;   -- Character clock
     ci_reset          : in std_logic;   -- Reset (asynchronous, active low)


@@ 133,31 132,10 @@ begin  -- architecture a1
     end if;
   end process set_state;
 
-  synced_subclass_0: if SUBCLASSV = 0 generate
-    set_synced: process(ci_frame_clk, ci_reset) is
-    begin
-      if ci_reset = '0' then
-        co_synced <= '0';
-      elsif ci_frame_clk'event and ci_frame_clk = '1' then
-        co_synced <= synced;
-      end if;
-    end process set_synced;
-  end generate synced_subclass_0;
-
-  synced_subclass_1: if SUBCLASSV = 1 generate
-    set_synced: process(ci_multiframe_clk, ci_reset) is
-    begin
-      if ci_reset = '0' then
-        co_synced <= '0';
-      elsif ci_multiframe_clk'event and ci_multiframe_clk = '0' then
-        co_synced <= synced;
-      end if;
-    end process set_synced;
-  end generate synced_subclass_1;
-
   synced <= '0' when reg_state = INIT or (reg_state = CGS and reg_k_counter < SYNC_COUNT) else '1';
   full_synchronization <= '0' when synced = '0' or correct_8b10b_characters < FULL_SYNCHRONIZATION_AFTER else '1';
 
+  co_synced <= synced;
   co_state <= reg_state;
   -- TODO: add ILAS errors, add CGS error in case sync does not happen for long
   -- time

@@ 61,6 61,9 @@ entity jesd204b_link_rx is
 end entity jesd204b_link_rx;
 
 architecture a1 of jesd204b_link_rx is
+
+  signal reg_synced : std_logic;
+  signal next_synced : std_logic;
   -- == DATA LINK ==
   -- outputs
   signal data_link_ready_vector : std_logic_vector(L-1 downto 0) := (others => '0');


@@ 119,7 122,33 @@ architecture a1 of jesd204b_link_rx is
   end function ConfigsMatch;
 begin  -- architecture a1
   -- nsynced is active LOW, set '0' if all ready
-  co_nsynced <= '0' when data_link_synced_vector = all_ones else '1';
+  nsynced_subclass_0: if SUBCLASSV = 0 generate
+    set_nsynced: process (ci_frame_clk, ci_reset) is
+    begin  -- process set_nsynced
+      if ci_reset = '0' then              -- asynchronous reset (active low)
+        co_nsynced <= '1';
+      elsif ci_frame_clk'event and ci_frame_clk = '1' then  -- rising clock edge
+        co_nsynced <= '1';
+        if data_link_synced_vector = all_ones then
+          co_nsynced <= '0';
+        end if;
+      end if;
+    end process set_nsynced;
+  end generate nsynced_subclass_0;
+
+  nsynced_subclass_1: if SUBCLASSV = 1 generate
+    set_nsynced: process (ci_multiframe_clk, ci_reset) is
+    begin  -- process set_nsynced
+      if ci_reset = '0' then              -- asynchronous reset (active low)
+        co_nsynced <= '1';
+      elsif ci_multiframe_clk'event and ci_multiframe_clk = '1' then  -- rising clock edge
+        co_nsynced <= '1';
+        if data_link_synced_vector = all_ones then
+          co_nsynced <= '0';
+        end if;
+      end if;
+    end process set_nsynced;
+  end generate nsynced_subclass_1;
 
   -- start lanes data after all are ready
   start_lanes_subclass_0: if SUBCLASSV = 0 generate


@@ 161,6 190,9 @@ begin  -- architecture a1
   co_error <= not ConfigsMatch(lane_configuration_array);
   co_correct_data <= co_frame_state.user_data;
 
+  next_synced <= '1' when data_link_synced_vector = all_ones else '0';
+  request_sync <= request_sync_event or ci_request_sync;
+
   data_links : for i in 0 to L-1 generate
     data_link_layer : entity work.data_link_layer
       generic map (