library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is

end entity counter_tb;

architecture behav of counter_tb is
  signal clk : std_logic := '0';
  signal rst : std_logic := '0';
  signal led : std_logic;
  signal count : std_logic_vector(9 downto 0);
  signal run : std_logic := '1';
begin  -- architecture behav

  clk <= not clk and run after 5 ns;
  rst <= '0', '1' after 15 ns;

  dut : entity work.counter
    port map (
      clk_i  => clk,
      rst_in => rst,
      led_o  => led,
    count_o  => count);

  process is
  begin  -- process
    wait until count'event;
    report "count: " & to_string(count) & ", led: " & to_string(led);
  end process;

  process is
  begin  -- process
    wait for 10 us;
    run <= '0';
    wait;
  end process;

end architecture behav;