9 files changed, 191 insertions(+), 0 deletions(-)

A .envrc
A channels.scm
A guix
A guix.scm
A manifest.scm
A projects/counter/Makefile
A projects/counter/counter.pcf
A projects/counter/src/counter.vhd
A projects/counter/tb/counter_tb.vhd

@@ 1,3 @@
+source ./guix/etc/profile
+use guix
+export yosys='yosys -m '$(guix shell -m ./manifest.scm -- bash -c 'echo $GUIX_ENVIRONMENT/lib/yosys/ghdl.so')

@@ 1,20 @@
+(cons*
+ (channel
+  (name 'guix-science)
+  (url "https://codeberg.org/guix-science/guix-science")
+  (branch "master")
+  (introduction
+   (make-channel-introduction
+    "b1fe5aaff3ab48e798a4cce02f0212bc91f423dc"
+    (openpgp-fingerprint
+     "CA4F 8CF4 37D7 478F DA05  5FD4 4213 7701 1A37 8446"))))
+ (channel
+  (name 'electronics)
+  (url "https://git.sr.ht/~csantosb/guix.channel-electronics")
+  (branch "main")
+  (introduction
+    (make-channel-introduction
+      "ba1a85b31202a711d3e3ed2f4adca6743e0ecce2"
+      (openpgp-fingerprint
+        "DA15 A1FC 975E 5AA4 0B07  EF76 F1B4 CAD1 F94E E99A"))))
+ %default-channels)

@@ 1,1 @@
+/gnu/store/a1w6gfafg2ydjjfdsa9pw9rzvkr0vi62-profile<
\ No newline at end of file

@@ 1,11 @@
+(use-modules
+ (guix ui)
+ (gnu packages package-management))
+
+(define (load-channels file)
+  (load* file (make-user-module '((guix channels)))))
+
+(packages->manifest
+ (list
+  (guix-for-channels
+   (load-channels "./channels.scm"))))

@@ 1,13 @@
+(specifications->manifest
+ (list
+  "ghdl-clang"
+  "ghdl-yosys-plugin"
+  "nvc"
+  "yosys"
+  "icestorm"
+  "nextpnr-ice40"
+
+  "python"
+  "python-vunit"
+
+  "make"))

@@ 1,50 @@
+YOSYS?=yosys
+NEXTPNR?=nextpnr-ice40
+NEXTPNR_ARGS=--hx1k --package tq144
+CELLS?=`yosys-config --datdir/ice40/cells_sim.v`
+
+VLOG?=vlog
+VCOM?=vcom
+VSIM?=vsim
+
+TOP?=counter
+
+.PHONY: logs
+logs: out/counter-pre-synth.log out/counter-post-synth.log out/counter-post-pnr.log
+
+out/counter-synth.json: src/counter.vhd
+	$(YOSYS) -p "ghdl $^ -e counter; hierarchy -check -top counter; proc; synth_ice40; write_json $@"
+out/counter-synth.v: out/counter-synth.json
+	$(YOSYS) -p "read_json $<; write_verilog $@"
+
+out/counter-pnr.asc: out/counter-synth.json
+	$(NEXTPNR) $(NEXTPNR_ARGS) --top counter --json $< --pcf counter.pcf --asc $@
+
+out/counter-pnr.json: out/counter-synth.json
+	$(NEXTPNR) $(NEXTPNR_ARGS) --top counter --json $< --pcf counter.pcf --write $@
+
+out/counter-pnr.v: out/counter-pnr.json
+	$(YOSYS) -p "read_json $<; write_verilog $@"
+	sed -i 's/module top/module counter/' $@
+
+out/counter-pnr.sdf: out/counter-synth.json
+	$(NEXTPNR) $(NEXTPNR_ARGS) --top counter --json $< --pcf counter.pcf --sdf $@
+
+out/counter-pre-synth.log: src/counter.vhd tb/counter_tb.vhd
+	rm -rf work transcript
+	$(VCOM) -2008 $^
+	$(VSIM) counter_tb -batch -do 'run -all; quit' -logfile $@
+	rm -rf work transcript
+
+out/counter-post-synth.log: out/counter-synth.v tb/counter_tb.vhd
+	rm -rf work transcript
+	$(VLOG) -sv $< $(CELLS)
+	$(VCOM) -2008 tb/counter_tb.vhd
+	$(VSIM) counter_tb -t 1ps -batch -do 'run -all; quit' -logfile $@
+	rm -rf work transcript
+
+out/counter-post-pnr.log: out/counter-pnr.v out/counter-pnr.sdf
+	rm -rf work transcript
+	$(VLOG) -sv $< $(CELLS)
+	$(VCOM) -2008 tb/counter_tb.vhd
+	$(VSIM) counter_tb -t 1ps -batch -do 'run -all; quit' -logfile $@ -sdfmax dut/=out/counter-pnr.sdf -suppress 3250,12090,12088

@@ 1,16 @@
+# full iCEstick pinout:
+# http://www.pighixxx.com/test/portfolio-items/icestick/
+
+set_io led_o 99
+set_io count_o[0] 98
+set_io count_o[1] 97
+set_io count_o[2] 96
+set_io count_o[3] 95
+set_io count_o[4] 94
+set_io count_o[5] 93
+set_io count_o[6] 24
+set_io count_o[7] 31
+set_io count_o[8] 32
+set_io count_o[9] 33
+set_io clk_i 21
+set_io rst_in 22<
\ No newline at end of file

@@ 1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+
+  port (
+    clk_i   : in  std_logic;
+    rst_in  : in  std_logic;
+    count_o : out std_logic_vector(9 downto 0);
+    led_o   : out std_logic);
+
+end entity counter;
+
+architecture a1 of counter is
+  signal curr_count : unsigned(9 downto 0);
+  signal next_count : unsigned(9 downto 0);
+begin  -- architecture a1
+
+  set_count: process (clk_i) is
+  begin  -- process set_count
+    if rising_edge(clk_i) then          -- rising clock edge
+      if rst_in = '0' then              -- synchronous reset (active low)
+        curr_count <= (others => '0');
+      else
+        curr_count <= next_count;
+      end if;
+    end if;
+  end process set_count;
+
+  next_count <= curr_count + 1 when curr_count /= "1111111111" else
+                (others => '0');
+
+  count_o <= std_logic_vector(curr_count);
+  led_o <= curr_count(9);
+
+end architecture a1;

@@ 1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter_tb is
+
+end entity counter_tb;
+
+architecture behav of counter_tb is
+  signal clk : std_logic := '0';
+  signal rst : std_logic := '0';
+  signal led : std_logic;
+  signal count : std_logic_vector(9 downto 0);
+  signal run : std_logic := '1';
+begin  -- architecture behav
+
+  clk <= not clk and run after 5 ns;
+  rst <= '0', '1' after 15 ns;
+
+  dut : entity work.counter
+    port map (
+      clk_i  => clk,
+      rst_in => rst,
+      led_o  => led,
+    count_o  => count);
+
+  process is
+  begin  -- process
+    wait until count'event;
+    report "count: " & to_string(count) & ", led: " & to_string(led);
+  end process;
+
+  process is
+  begin  -- process
+    wait for 10 us;
+    run <= '0';
+    wait;
+  end process;
+
+end architecture behav;