~ruther/vhdl-spi-2

ref: c7e760505de065eff00a855e1ebf55c0bbe8e192 vhdl-spi-2/hdl_spi/.gitignore -rw-r--r-- 94 bytes
c7e76050 — Rutherther fix: master_ctrl_rst_n shou be used, not master_ctrl_rst, start_clock is split 1 year, 4 days ago 
                                                                                
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modelsim.ini
sim_build/
__pycache__/
transcript
vsim.wlf
vsim_stacktrace.vstf
core
results.xml