~ruther/vhdl-spi-2

ref: abfea28a8a2555ec22557089a359b3f2b6fd5f23 vhdl-spi-2/stm_spi_funduino/libs/CMSIS_6/.gitignore -rw-r--r-- 540 bytes
abfea28a — Rutherther fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising 1 year, 1 month ago 
                                                                                
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*.junit
**/__pycache__
CMSIS/Documentation/html
CMSIS/Documentation/Doxygen/**/*.dxy
CMSIS/Core/Test/*.o
CMSIS/Core/Test/*.xunit
CMSIS/Core/Test/.lit_test_times.txt
CMSIS/CoreValidation/Project/*.zip
CMSIS/CoreValidation/Project/*.junit
CMSIS/CoreValidation/Project/*.clangd
CMSIS/CoreValidation/Project/Validation.*/
CMSIS/CoreValidation/Project/Bootloader.*/
CMSIS/CoreValidation/Project/build
CMSIS/CoreValidation/Project/RTE/_**/*
*.cbuild-idx.yml
*.uvguix.*
*.uvmpw.uvgui.*
*.zip
*.bak
build
output
linkchecker-out.csv
.DS_STORE
*.tmp