~ruther/vhdl-spi-2

ref: 21e3de55dc52c5a3a0d5b5afc70ab42cdff0ff65 vhdl-spi-2/stm_spi_funduino/.gitmodules -rw-r--r-- 209 bytes
21e3de55 — Rutherther fix: master didn't go to invalid data when data are read on first cycle of ready 3 months ago 
                                                                                
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[submodule "CMSIS"]
	path = libs/CMSIS_6
	url = https://github.com/ARM-software/CMSIS_6
[submodule "cmsis_device_h7"]
	path = libs/cmsis_device_h7
	url = https://github.com/STMicroelectronics/cmsis_device_h7/
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