fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising

fix: csn was rising too soon for divisors > 2

fix: short last sck pulse on slower clock

fix: selected_divisor range

fix: clkgen for various phases and polarities

fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3

feat: implement initial hdl_spi