~ruther/vhdl-spi-2

ref: e9f10c1ef38e201d7a475ca12c49aaf876453b6d vhdl-spi-2/hdl_spi/src/spi_clkgen.vhd -rw-r--r-- 2.5 KiB
55fdca2b — Rutherther 9 months ago 
fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3
dc0e370a — Rutherther 9 months ago 
feat: implement initial hdl_spi