~ruther/vhdl-spi-2

ref: 55fdca2b9c6e0468cb4a26040791ad6faf48b481 vhdl-spi-2/hdl_spi/src/spi_clkgen.vhd -rw-r--r-- 2.5 KiB
55fdca2b — Rutherther 3 months ago 
fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3
dc0e370a — Rutherther 3 months ago 
feat: implement initial hdl_spi
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