~ruther/vhdl-spi-2

ref: cd5b4c89d9709deee774c761e72dd0e6a61ab1a3 vhdl-spi-2/hdl_spi/src/spi_clkgen.vhd -rw-r--r-- 2.5 KiB
55fdca2b — Rutherther 9 months ago 
fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3
dc0e370a — Rutherther 9 months ago 
feat: implement initial hdl_spi