~ruther/vhdl-spi-2

ref: 5c7a8bb412b0f4dc78f9b891819452e477869678 vhdl-spi-2/hdl_spi/src/spi_clkgen.vhd -rw-r--r-- 2.5 KiB
55fdca2b — Rutherther 9 months ago 
fix: sck generation

Sampling and changing was offset by one clock,
which is unnecesary. The clock wasn't correct
frequency, ie. divisor 2 led to division by 3
dc0e370a — Rutherther 9 months ago 
feat: implement initial hdl_spi