~ruther/vhdl-i2c

ref: b7600b1d64f28e6c5a661cb853a0cdfbb0b0ee6c vhdl-i2c/src/utils/clock_divider.vhd -rw-r--r-- 1.0 KiB 
fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

fix: make sure clock divider has 50 % duty cycle

fix: many changes