fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

feat: simplify bcd counter

fix: make sure clock divider has 50 % duty cycle

fix: many changes

refactor: use 'H' std_logic state instead of custom pull up type

fix: activate pad_io in open drain on enable = 1

fix: correct delay pulses length

chore: use integer instead of natural when with range

feat: add possibility for 0 delay in delay entity

fix: compilation errors

feat: add utility entities

Delay, metastability filter, open drain buffer, synchronous edge detector