~ruther/verilog-riscv-semestral-project (feat/misaligned-reads): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: feat/misaligned-reads verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

89e944c0 — Rutherther fix: sign extend only when misaligned access 1 year, 3 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git