~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/src/stages/writeback.sv -rw-r--r-- 402 bytes
fb02ebb2 — Rutherther Merge pull request #2 from Rutherther/feat/misaligned-reads 2 years ago 
                                                                                
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import cpu_types::*;

module writeback(

  input         clk,

  output [4:0]  reg_a_write,
  output        reg_we,
  output [31:0] reg_write,

  input         stage_status_t stage_in
);
  assign reg_a_write = stage_in.data.address;
  assign reg_we = stage_in.valid && stage_in.data.valid && stage_in.instruction.reg_we; // stage_in.data.address != 0
  assign reg_write = stage_in.data.data;
endmodule