~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/src d---------
fb02ebb2 — Rutherther Merge pull request #2 from Rutherther/feat/misaligned-reads 1 year, 4 months ago
..
-rwxr-xr-x
alu.sv
1.0 KiB
-rwxr-xr-x
control_unit.sv
3.3 KiB
-rwxr-xr-x
cpu.sv
3.9 KiB
-rw-r--r--
cpu_singlecycle.sv
4.2 KiB
-rwxr-xr-x
cpu_types.sv
1.9 KiB
-rwxr-xr-x
file_program_memory.sv
319 bytes
-rw-r--r--
forwarder.sv
1.2 KiB
-rwxr-xr-x
instruction_decoder.sv
7.1 KiB
-rwxr-xr-x
program_counter.sv
383 bytes
-rwxr-xr-x
ram.sv
1.1 KiB
-rwxr-xr-x
register_file.sv
828 bytes
d---------
stages/
Do not follow this link