~ruther/verilog-riscv-semestral-project (f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2): tests/official/env/p/link.ld

~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes

f8e4e3ed — Rutherther Merge pull request #1 from Rutherther/feat/pipeline 1 year, 5 months ago

SECTIONS
{
  .text.init = 0x0;
}