~ruther/verilog-riscv-semestral-project

ref: e5d2c0c5de0541507c602b1d9a5cff2a0cc88494 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 332 bytes
e5d2c0c5 — Rutherther tests: add simple ma.c program for testing misaligned access 2 years ago 
                                                                                
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src/cpu_types.sv
src/instruction_decoder.sv
src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv

src/forwarder.sv

src/stages/fetch.sv
src/stages/decode.sv
src/stages/execute.sv
src/stages/memory_access.sv
src/stages/writeback.sv

src/ram.sv
src/cpu.sv
src/file_program_memory.sv

testbench/tb_cpu_program.sv