~ruther/verilog-riscv-semestral-project

ref: e5d2c0c5de0541507c602b1d9a5cff2a0cc88494 verilog-riscv-semestral-project/programs/ma.c -rw-r--r-- 282 bytes
e5d2c0c5 — Rutherther tests: add simple ma.c program for testing misaligned access 1 year, 4 months ago 
                                                                                
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int main() {

    // 0x0F000000
    __asm__(" \
      addi x1, x0, 0x0F\n \
      sll x1, x1, 24\n    \
      addi x1, x1, 0x0A\n \
      sw x1, 1(x0)\n      \
      lw x2, 1(x0)\n      \
      nop\n               \
      nop\n               \
      ebreak\n            \
    ");
}
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