~ruther/verilog-riscv-semestral-project (e5d2c0c5de0541507c602b1d9a5cff2a0cc88494): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: e5d2c0c5de0541507c602b1d9a5cff2a0cc88494 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

e5d2c0c5 — Rutherther tests: add simple ma.c program for testing misaligned access 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git