~ruther/verilog-riscv-semestral-project (df876b38b787b7f1e9120775311a0b1a17e2758b): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

df876b38 — Rutherther chore: extend memory 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}