~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
df876b38 — Rutherther chore: extend memory 2 years ago 
                                                                                
1
2
3
4
5
6
7
8
9

.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop