~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 649 bytes
df876b38 — Rutherther chore: extend memory 1 year, 5 months ago 
                                                                                
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void main()
{
    int *result_address = 0;
    int a = 1;
    int b = 5;

    if (a < b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a >= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a != b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a == b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a <= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a > b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }
}
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