~ruther/verilog-riscv-semestral-project

ref: ca9604e2c8a9c44ccba5223ef095d84cd618bbe1 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
ca9604e2 — Rutherther fix: offset ram by bytes, not bits 1 year, 7 months ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd
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