~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/tests/custom d---------
c5e322db — Rutherther fix: use reg for procedural assignments 1 year, 6 months ago
..
-rwxr-xr-x
custom_tests.py
1.9 KiB
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