~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
c5e322db — Rutherther fix: use reg for procedural assignments 1 year, 4 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop
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