~ruther/verilog-riscv-semestral-project

ref: b7fa590c93b0d8e3e647fb08ecf033e314ece360 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
b7fa590c — Rutherther chore: add cpu types for various sources 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd