~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
aeab4038 — Rutherther feat: add forwarding signal for better debugging 2 years ago 
                                                                                
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SECTIONS
{
  .text.init = 0x0;
}