~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/src/program_counter.sv -rwxr-xr-x 383 bytes
aeab4038 — Rutherther feat: add forwarding signal for better debugging 1 year, 4 months ago 
                                                                                
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// + 4 normally
// or if should jump, jump to given address (either pc + imm or rs1 + imm)

module program_counter(
  input                    clk,
  input                    rst_n,
  input [WIDTH - 1:0]      pc_next,
  output reg [WIDTH - 1:0] pc
);
  parameter WIDTH = 12;

  always_ff @ (posedge clk)
    if (rst_n == 1'b0)
      pc <= 0;
    else
      pc <= pc_next;

endmodule
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