~ruther/verilog-riscv-semestral-project (aeab403896e168bc0c44a65883d46bb96689b7fb): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

aeab4038 — Rutherther feat: add forwarding signal for better debugging 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git