~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
adfdc041 — Rutherther feat: add branches.c test 2 years ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop