~ruther/verilog-riscv-semestral-project (a400aceb574400fad6b269927793a5c13aab647c): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

a400aceb — Rutherther feat: make RAM word aligned, add byte_enable 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}