~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 95 bytes
a400aceb — Rutherther feat: make RAM word aligned, add byte_enable 1 year, 5 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 124
    call main
_loop:
    ebreak
    j _loop
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