~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 468 bytes
a400aceb — Rutherther feat: make RAM word aligned, add byte_enable 1 year, 5 months ago 
                                                                                
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void main()
{
    int a = 1;
    int b = 5;
    int c = 0;

    if (a < b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a >= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a != b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a == b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a <= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a > b) {
        c = 1;
    } else {
        c = 2;
    }

}
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