~ruther/verilog-riscv-semestral-project

ref: 9c81ece23403b5cc0265b8012f82c935f3e64822 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes
9c81ece2 — Rutherther chore: add gitignore 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/