~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago 
                                                                                
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{
  .text.init = 0x0;
}
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