~ruther/verilog-riscv-semestral-project (914e69e6c0df1f4e3f33718891c838e42fe535b1): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}