~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 381 bytes
914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago
                                                                                
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.globl main
.globl _start
.globl __start

.option norelax

.text

__start:
_start:
    .option push
    .option norelax
    la gp, __global_pointer$
    .option pop

    addi sp, x0, 1020
    addi a0, zero, 0
    addi a1, zero, 0
    call main
quit:
	addi    a0, zero, 0
	addi    a7, zero, 93  /* SYS_exit */
	ecall
loop:
    ebreak
    beq     zero, zero, loop

.bss

.end _start
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