~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 350 bytes
914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")

MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

PROVIDE( __global_pointer$ = 0x0 );

SECTIONS
{
	.text : {
        *(.text._start);
        *(.text);
        *(.text.*);
    } > ram
    .bss : {
        *(.bss)
        *(COMMON)
        *(.bss.*)
    } > ram
}
Do not follow this link