~ruther/verilog-riscv-semestral-project (914e69e6c0df1f4e3f33718891c838e42fe535b1): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago

1
2
3

[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git