~ruther/verilog-riscv-semestral-project (914e69e6c0df1f4e3f33718891c838e42fe535b1): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

914e69e6 — Rutherther refactor: save pc + 4 in stages 1 year, 3 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/