~ruther/verilog-riscv-semestral-project (7d544e62c57a7e944d1572d147f7b271333a75aa): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

7d544e62 — Rutherther chore: pass in full trace file instead of program name 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git