~ruther/verilog-riscv-semestral-project (7d544e62c57a7e944d1572d147f7b271333a75aa): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 7d544e62c57a7e944d1572d147f7b271333a75aa verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

7d544e62 — Rutherther chore: pass in full trace file instead of program name 1 year, 7 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/