~ruther/verilog-riscv-semestral-project (740085c87e5cdab5e4d96e696df87f4a30e6f09f): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 6 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}