~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 6 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop
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